In multiprocessor systems of loosely coupled kind operating with digital switching units, in single-processor or multiprocessor systems handling packet switching, and generally when a processor is to exchange messages with a PCM signal path or with other processors, it is necessary to have bidirectional gates enabling data to be transferred from the processor to the signal path and vice versa, according to predetermined dialogue protocols. PCM frames encompassing 32 channels, operating at 64-Kbit/s, are customarily transmitted on any signal path; the No. 0 time slot of a frame normally serves to carry channel addresses and sync signals.
On the one hand it is of interest to dispose of a large number of such paths, e.g. in case of a loosely coupled multiprocessor system operating in the packet-switching domain. In this case each processor needs access gates for the data to be transferred to and from a PCM terminal as well as multichannel routes leading to the other processors. On the other hand, the present state of the art gives rise to numerous problems when the number of such gates is high. In fact, each gate acts as a peripheral unit of a rather complex type for the processor; it must handle the lowest levels of the communication protocol which the processor could not do since that would entail too many repetitive tasks.
Data interchange between the periphery and the processor memory via the usual line multiple or bus can take place in various ways, i.e. by line sensing, interrupt and direct memory access; line-sensing and interrupt procedures may involve storage in the peripheral unit at a byte or a message level, in a memory of FIFO (first in, firt out) or double-access type, all for both transmission directions.
In case of a line-sensing operation a data storage at the byte level in the interface is not very convenient. Thus, the processor must continuously execute tests of data ready and of data received, as well as check on the line conditions; positive tests are then to be followed by an instruction of byte transfer which is a cumbersome procedure when there are many data to be temporarily stored.
When the data are to be stored at the message level, each interface is to be equipped with a memory sufficient to contain two departing and two arriving messages in order to ensure the complete use of a channel. The tests on the arriving messages must then be rather frequent in order to avoid useless waits when the message is short.
With interrupt procedure, if the data to be stored are organized into bytes, it is difficult to meet the interrupt requirements during traffic peaks, whereas if the data are organized into messages, the storage is still burdensome. Test elimination entails the introduction of many interrupt sources, whose number is limited by the processor structure.
With either of the aforedescribed techniques, if a message is to be forwarded through a plurality of output gates, it is to be transferred by the processor into the buffer of each of them; if a message is to transit from one gate to another, it must be first transferred from the input buffer to the memory and from the latter into the output buffer. Furthermore, the output buffer --especially if it is of the FIFO type--cannot hold messages waiting to be checked unless it has a very high storage capacity.
With use of the "direct memory access" technique the storage in the peripheral unit is no longer necessary; this is an advantage, even though for each incoming channel there must be available a suitable memory area assigned from time to time by the processor and ready to receive a possible message. The requests for bus access to be satisfied by the processor are, however, very numerous, especially during peak traffic. Thus, just when the processor is to exhibit the maximum data-handling capacity, it often slackens while also having to control the message buffer even as the number of interrupt sources (or the number of tests to be carried out) necessary for obtaining information relating to the received or transmitted complete messages remains high.
In all these cases, furthermore, there exists no possibility of on-line checking on the proper functioning of the interfaces, but the service has to be interrupted on the respective channel for the duration of such a test.